System for filling outlines by addition and subtraction according to start and end positions of the outlines

ABSTRACT

An image outline filling system comprises an image outline memory for storing start positions and end positions of image outlines, and a controllable arithmetic circuit which changes its output status in a positive direction at a start position of the image outlines and changes the output status in a negative direction at a end position of the image outlines. By filling a region in which the output status has a value of the positive direction, the image outline whose inside is filled is obtained.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an image processing system and, moreparticularly, to an image processing system for filling the inside of animage outline that is synthesized from a plurality of outlines.

2. Description of the Related Art

A method for synthesizing a plurality of image outlines and filling theinside thereof is disclosed in Japanese Patent Laid-open No. 1-164992.In this method, individual image outlines are filled and then the filledimages are synthesized. As shown in FIG. 1, two image outlines generatedby an outline generator 1 are stored in work memories 2 and 3,respectively. The insides of the two image outlines stored in the workmemories 2 and 3 are filled under the control of a transfer controller 4by filling circuits 5 and 6, respectively, and the filled image outlinesare then transferred through an OR circuit 7 to a bit map memory 8.

An example of the concrete operation of the above-described method isshown in FIG. 2. Two image Outlines are stored in the work memories 2and 3, and the insides thereof are filled by the filling circuits 5 and6, respectively. The filled image outlines are overlapped by the ORcircuit 7 and stored in the bit map memory 8.

However, in the above-described method, if the number of image outlinesto be synthesized is increased, it will be necessary to provide the workmemories and the filling circuits corresponding in number to the imageoutlines. The conventional method therefore has the disadvantage thatthe scale of the circuitry will be increased extremely if a large numberof image outlines is synthesized.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide afilling system which makes it possible to fill any image outline withsmall-scale circuitry.

Another object of the present invention is to provide a filling systemwhich makes it possible to fill a synthesized image outline withsmall-scale circuitry independent of the number of image outlines to besynthesized.

To achieve the above objects, there is provided according to the presentinvention an image outline filling system which comprises an imageoutline memory for storing start positions and end positions of an imageoutline, and a controllable arithmetic circuit which is capable ofchanging its output status on a scanning line in a positive or anegative direction. The controllable arithmetic circuit changes itsoutput status at a line start position of the image outline in thepositive direction and changes the output status at a line end positionin the negative direction. In other words, even if the image outlineswere synthesized from many outlines, the number of syntheses would beexpressed as an output status of the controllable arithmetic circuit. Byfilling a scanning line region in which the output status of thecontrollable arithmetic circuit has a value in the positive direction,there can be obtained an image outline whose inside is filled.

It is preferable that the image outline memory comprises a start outlinememory for storing line start positions of the image outline, and an endoutline memory for storing end positions of the same image outline.

The controllable arithmetic circuit may comprise an adder-subtracter forperforming addition operations at line start positions and subtractionoperations at line end positions. Preferably, a plurality ofadder-subtracters and a single latch circuit are connected in series,and the output status of the controllable arithmetic circuit can beexpressed by the output values of the respective adder-subtracters. Inthis configuration, a scanning line is processed by repeatedly operatingthe adder-subtracters through the latch circuit. It is thereforepreferable that the number of data bits on a scanning line be a multipleof the number of adder-subtracters.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and advantages will become apparent from thefollowing detailed description when read in conjunction with theaccompanying drawings wherein:

FIG. 1 is a block diagram view showing a conventional outline fillingsystem;

FIG. 2 is a flowchart showing a conventional outline filling methodwhich is carried out by the system of FIG. 1;

FIG. 3 is a block diagram showing an embodiment of an outline fillingsystem according to the present invention;

FIG. 4 is a schematic view showing a synthesized image outline used toexplain the operation of the embodiment of the present invention;

FIG. 5 is a graph showing how the output status of the controllableadder-subtracter is changed in the present embodiment;

FIG. 6 is a detailed block diagram of the present embodiment;

FIGS. 7A and 7B are schematic bit map diagrams showing two imageoutlines generated by the outline generator of the present embodiment;

FIG. 7C is a schematic bit map diagram showing the bit map state inwhich the two image outlines in FIGS. 7A and 7B are synthesized;

FIG. 8A is a schematic bit map diagram showing the start position of asynthesized image outline stored in the outline start position memory ofthe present embodiment;

FIG. 8B is a schematic bit map diagram showing the end position of asynthesized image outline stored in the outline end position memory ofthe present embodiment;

FIG. 9 is a data bit state diagram showing a data processing operationof the present embodiment; and

FIG. 10 is a bit map diagram of a synthesized outline filled by thepresent embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 3, there is shown a preferred embodiment of a fillingsystem in accordance with the present invention. Outline coordinate datagenerated by an outline generator 100 is divided into outline startposition data and outline end position data by a start/end data divider101. The outline start position data and the outline end position dataare stored in the form of a line data into an outline start positionmemory 102 and an outline end position memory 103, respectively. Thestart/end data divider 101 discriminates between the outline startposition data and the outline end position data, depending on which adifferential value of the outline coordinate data is positive ornegative.

A controllable adder-subtracter 104 receives an addition control signaland a subtraction control signal from the outline start position memory102 and the outline end position memory 103, respectively. The additioncontrol signal is comprised of the outline start position data and thesubtraction control signal is comprised of the outline end positiondata. Receiving these control signals, the controllable adder-subtracter104 performs an addition operation when the addition control signalindicative of an outline start position is input and performs asubtraction operation when the subtraction control signal indicative ofan outline end position is input. Through these addition and subtractionoperations, the controllable adder-subtracter 104 outputs a value of 1or more in the region between the first outline start position and thelast outline end position of a certain scanning line and outputs a valueof 0 at positions other than that region. A filled image data generationcircuit 105 receives the output value of the controllableadder-subtracter 104 for each scanning line and fills regions having avalue of 1 or more. All of the filled regions are replaced, for example,by `1`, and output to an image data memory 106. The image data memory106 stores therein the filled line data in sequence and forms bit mapimage data.

FIG. 4 illustrates a case in which the outline generator 100 generatesthe outline coordinate data in which two outlines are synthesized.Since, as shown in the figure, a start position and an end position ofeach image outline exist on a certain scanning line, two start positionsand two end positions are stored in the outline start position memory102 and the outline end position memory 103, respectively. Note that theoutline coordinate data is divided by the start/end data divider 101such that the number of start positions is always equal to the number ofend positions on any line. Such start position data and end positiondata are output in scanning lines to the controllable adder-subtracter104 as addition and subtraction parameters.

As shown in FIG. 5, the output status of the controllableadder-subtracter 104 is increased by one unit each time bit data `1`indicative of a start position is input, and is decreased by one uniteach time bit data `1` indicative of an end position is input.Therefore, the output value of the controllable adder-subtracter 104 isincremented from "0" to "1" by the first start position S1 and furtherincremented by the next start position S2, and the output value goes to"2". The output value is decremented by the first end position E1 and isreturned to "0" by the last end position E2. The region having outputvalues of 1 or more is therefore formed on the scanning line between thefirst start position S1 and the last end position E2, and the region areto be filled.

The above-described operation of the controllable adder-subtracter 104is applicable not only to the synthesis of two image outlines but alsoto the synthesis of an arbitrary number of image outlines. Moreparticularly, since the number of start positions (also end positions)is equal to that of synthesized image outlines, an output value of thecontrollable adder-subtracter 104 is incremented each time a startposition is input and decremented each time an end position is input,and, finally, the output value is returned to "0". Therefore, only theinside positions of the outermost outline of a synthesized outline havean output value of 1 or more, and such a region is to be filled.

The controllable adder-subtracter 104 may be comprised of a singlecontrollable adder-subtracter and can also be comprised of a pluralityof controllable adder-subtracters which are connected in series. Thenumber of data bits of any scanning line is a multiple of the number ofthe controllable adder-subtracters. Note that since, in the case of aplurality of controllable adder-subtracters, the addition andsubtraction operations are required repeatedly to cover all of the databits of one line, a latch circuit is further required to be connected tothe controllable adder-subtracters in series.

A circuit construction in which a frame of image data is 8 bits×8 linesand four controllable adder-subtracters are used will hereinafter bedescribed as a concrete example of this embodiment to make thedescription simpler.

As shown in FIG. 6, the controllable adder-subtracter 104 comprises asingle latch circuit 201 and four controllable adders 202 to 205. Thelatch circuit 201 comprises a flip-flop, and output terminals F0 to F3are connected to input terminals B10 to B13 of the adder 202,respectively. The adders 202 to 205 are likewise connected in series.Output terminals A40 to A43 of the last adder 205 are connected to inputterminals E0 to E3 of the latch circuit 201, respectively.

Output terminals D10 to D13 of the outline start position memory 102 areconnected to the addition control terminals of the adders 202 to 205,respectively, and output terminals D20 to D23 of the outline endposition memory 103 are connected to the subtraction control terminalsof the adders 202 to 205, respectively.

The filled image data generation circuit 105 comprises 0R gates 206 to209. Output terminals A10 to A13 of the adder 202 are connected to theinput terminals of the OR gate 206, respectively. Likewise, the outputterminals of the adders 203 to 205 are connected to the input terminalsof the OR gates 207 to 209, respectively. Also, the respective outputterminals D20 to D23 of the outline end position memory 103 areconnected to the input terminals of the OR gates 206 to 209. The outputterminals of the OR gates 206 to 209 are connected to input terminalsD30 to D33 of the image data memory 106, respectively.

A controller 107 outputs latch control signal C1 to the latch circuit201, data read control signal C2 to the outline start position memory102, data read control signal C3 to the outline end position memory 103,and image data write control signal C4 to the image data memory 106.

Operation

An operation in a case where the two image outlines shown in FIGS. 7Aand 7B are synthesized as shown in FIG. 7C will be described. Among theimage outline coordinate data generated by the outline generator 101,the outline start position data is stored in the outline start positionmemory 102, as shown in FIG. 8A, and the outline end position data isstored in the outline end position memory 103, as shown in FIG. 8B. For4th line of the outline data shown in FIGS. 8A and 8B, the fillingoperation of this embodiment will hereinafter be described withreference to FIG. 9.

First Step:

First, the controller 107 outputs the respective read control signals C2and C3 to the outline start position memory 102 and the outline endposition memory 103. This causes the outline start position memory 102and the outline end position memory 103 to output the respective linedata 301 and 302 (in this example, of the fourth line) to thecontrollable adder-subtracter 104. As shown in FIG. 9, the line data 301of `0110` is output from the output terminals D10 to D13 of the outlinestart position memory 102, and the line data 302 of `0000` is outputfrom the output terminals D20-D23 of the outline end position memory103.

Since an initial output value of the latch circuit 201 is "0" 4-bit data`0000` is input to the input terminals B10 - B13 of the adder 202. Afirst bit data `0` of the line data 301 is output from the outputterminal D10 of the outline start position memory 102 to the additioncontrol terminal of the adder 202, and a first bit data `0` of the linedata 302 is output from the output terminal D20 of the outline endposition memory 103 to the subtraction control terminal of the adder202. Therefore, the adder 202 does not perform any addition orsubtraction operation, outputting 4-bit data `0000` from the outputterminals A10-A13 and, consequently, the OR gate 206 will output a bitdata `0`.

Similarly, since the adder 203 receives 4-bit data `0000` from the adder202, a bit data `1` of D11 at the addition control terminal, and a bitdata `0` of D21 at the subtraction control terminal, the adder 203performs the addition operation and outputs 4-bit data `0001`, ordecimal numeral "1", from the output terminals A20-A23. Therefore, theOR gate 207 will output a bit data `1`. Since the adder 204 receivesdecimal numeral "1" from the adder 203, a bit data `1` of D12 at theaddition control terminal, and a bit data `0` at the subtraction controlterminal, the addition operation is performed to output 4-bit data`0010`, i.e. , decimal numeral "2", from the output terminals A30-A33.Therefore, the OR gate 208 will output a bit data `1`. Finally, sincethe adder 205 receives a decimal numeral "2" from the adder 204, a bitdata `0` of D13 at the addition control terminal, and a bit data `0` ofD23 at the subtraction control terminal, the adder 205 does not performany addition or subtraction operation, therefore outputs 4-bit data`0010`, i.e., decimal numeral "2", from the output terminals A40-A43.Therefore, the OR gate 209 will output a bit data `1`.

In this way, the respective output bits of the OR gates 206 to 209 are`0`, `1`, `1`, and `1` and output as filled image data 303 to the inputterminals D30 to D33 of the image data memory 106. The filling operationfor the first half of the 4th line data is completed.

Second Step:

Subsequently, the controller 107 outputs the latch control signal C1 tothe latch circuit 201 so that the output `0010` of the adder 205 islatched. The controller 107 further outputs the read control signals C2and C3 to the outline start position memory 102 and the outline endposition memory 103. In response to these signals C2 and C3, therespective memories 102 and 103 output the remaining line data 401 and402 to the controllable adder-subtracter 104.

Since the current output value of the latch circuit 201 is `0010`, ordecimal numeral "2", the adder 202 receives the output data `0010` atthe input terminals B10-B13. A first bit data `0` of the line data 401is output from the output terminal D10 of the outline start positionmemory 102 to the addition control terminal of the adder 202, and afirst bit data `0` of the line data 402 is output from the outputterminal D20 of the outline end position memory 103 to the subtractioncontrol terminal of the adder 202. Therefore, the adder 202 does notperform any addition or subtraction operation, outputting 4-bit data`0010` from the output terminals A10-A13 and, consequently, the OR gate206 will output a bit data `1`.

Similarly, since the adder 203 receives the 4-bit data `0010` from theadder 202, a bit data `0` of D11 at the addition control terminal, and abit data `1` of D21 at the subtraction control terminal, the adder 203performs the subtraction operation and outputs 4-bit data `0001`, ordecimal numeral "1" from the output terminals A20-A23. Therefore, the ORgate 207 will output a bit data `1`. Since the adder 204 receivesdecimal numeral "1" from the adder 203, a bit data `0` of D12 at theaddition control terminal, and a bit data `1` of D22 at the subtractioncontrol terminal, the subtraction operation is performed to output 4-bitdata `0000`, i.e., decimal numeral "0", from the output terminalsA30-A33. However, since the OR gate 208 receives bit data `1` from theterminal D22 of the end position memory 103, the output of the OR gate208 is `1`. Finally, since the adder 205 receives a decimal numeral "0"from the adder 204, bit data `0` of D13 at the addition controlterminal, and bit data `0` of D23 at the subtraction control terminal,the adder 205 does not perform any addition or subtraction operation,therefore outputs the 4-bit data `0000`, i.e., decimal numeral "0" fromthe output terminals A40-A43 Since the OR gate 209 inputs bit data "0"from the terminal D23 of the end position memory 103, the OR gate 209outputs bit data `0`.

In this way, the respective output bits of the OR gates 206 to 209 are`1`, `1`, `1` and `0` and output as filled image data 403 to the inputterminals D30 to D33 of the image data memory 106. The-filling operationfor the second half of the 4th line data is completed.

Through the above-described first and second steps, the fillingoperation of the 4th line data is performed to fill the region from thefirst outline start position (the 2nd data bit) to the last outline endposition (the 7th data bit). The above-described filling operation isrepeated from the 1st line to the 8th line so that the entire inside ofthe synthesized outline will be filled as shown in FIG. 10.

Although only one embodiment of the present invention has been describedherein, it will be apparent to those skilled in the art that the presentinvention may be embodied in many other specific forms without departingfrom the spirit or scope of the invention. For example, even if a frameof image data is comprised of 100 bits×100 lines, it would be apparentthat the filling operation can be executed with the same configurationas in FIG. 6. In addition, although, in this embodiment, two imageoutlines have been synthesized, the present invention is not limited tothis. Even if a number of image outlines were synthesized, the fillingoperation would be executed in the same way as in FIG. 6.

What is claimed is:
 1. An image signal processing system for filling theinsides of image outlines, comprising:controllable arithmetic meanscapable of changing its output status in either of a positive directionand a negative direction, the controllable arithmetic means changing theoutput status in one direction when a scanning position is coincidentwith a start position of the image outlines and changing the outputstatus in the opposite direction when the scanning position iscoincident with an end position of the image outlines, said controllablearithmetic means having first input means for receiving start positiondata of said image outlines and second input means for receiving endposition data of said image outlines; an outline start position memoryconnected to said first input means for storing the start position dataof the image outlines in scanning lines; and an outline end positionmemory connected to said second input means for storing the end positiondata of the image outlines in scanning lines; and filling means forfilling a region of the scanning line, the region comprising positionsin which the output status of the controllable arithmetic means has avalue of the one direction.
 2. An image signal processing system as setforth in claim 1, wherein the controllable arithmetic means comprises anaddition-subtraction means for performing an addition operation when thescanning position is coincident with the start position of the imageoutlines and performing a subtraction operation when the scanningposition is coincident with the end position of the image outlines. 3.An image signal processing system as set forth in claim 2, wherein theaddition-subtraction means comprises a latch circuit and a plurality ofadder-subtracters each performing the addition operation when thescanning position is coincident with the start position of the imageoutlines and performing the subtraction operation when the scanningposition is coincident with the end position of the image outlines, theplurality of adder-subtracters being cascade-connected and respectivelycorresponding to data bits of the scanning line, output terminals of thelast adder-subtracter being connected to input terminals of the latchcircuit, output terminals of the latch circuit being connected to inputterminals of the first adder-subtracter, and the output statuscomprising output values of the plurality of adder-subtracters.
 4. Animage signal processing system as set forth in claim 3, wherein thenumber of data bits of any scanning line is a multiple of the number ofthe adder-subtracters.
 5. An image signal processing system as set forthin claim 1, wherein the controllable arithmetic means comprises anaddition-subtraction means for performing an addition operation when thescanning position is coincident with the start position of the imageoutlines and performing a subtraction operation when the scanningposition is coincident with the end position of the image outlines. 6.An image signal processing system as set forth in claim 5, wherein theaddition-subtraction means comprises a latch circuit and a plurality ofadder-subtracters each performing the addition operation when thescanning position is coincident with the start position of the imageoutlines and performing the subtraction operation when the scanningposition is coincident with an end position of the image outlines, theplurality of adder-subtracters being cascade-connected and respectivelycorresponding to data bits of the scanning line, output terminals of thelast adder-subtracter being connected to input terminals of the latchcircuit, output terminals of the latch circuit being connected to inputterminals of the first adder-subtracter, and the output statuscomprising output values of the plurality of adder-subtracters.
 7. Animage signal processing system as set forth in claim 6, wherein thenumber of data bits of any scanning line is a multiple of the number ofthe adder-subtracters.
 8. An image signal processing system as set forthin claim 6, wherein the outline start position memory stores the startposition data comprising data bits of the number equal to that of theadder-subtracters, the outline end position memory stores the endposition data comprising data bits of the number equal to that of theadder-subtracters, the respective data bits of the start position dataare input to addition control terminals of the adder-subtracters, andthe respective data bits of the end position data are input tosubtraction control terminals of the adder-subtracters.
 9. An imagesignal processing system as set forth in claim 8, wherein the number ofdata bits of any scanning line is a multiple of the number of theadder-subtracters.
 10. An image signal processing method for filling theinsides of image outlines, the method comprising the steps of:storingstart position data of image outlines in scanning lines in an outlinestart position memory; storing end position data of image outlines inscanning lines in an outline end position memory; changing a controlstatus in one of a positive direction and a negative direction when ascanning position is coincident with a start position of the imageoutlines; changing the control status in the opposite direction when thescanning position is coincident with an end position of the imageoutlines; and filling a region of the scanning line, the regioncomprising positions in which the control status has a value of the onedirection.
 11. An image signal processing method as set forth in claim10, wherein the control status is changed in the positive direction whenthe scanning position is coincident with the start position of the imageoutlines and is changed in the negative direction when the scanningposition is coincident with the end position of the image outlines.